Explain the purposes of different types of primary memory

Registers, Cache (L1, L2, L3), RAM, ROM

Registers

• The fastest, smallest memory, built directly into the CPU.
• Store data, instructions, and addresses being actively executed.
• Volatile (requires power to maintain).
• Fundamental unit = word size, the size of a register. Typically holds 32 or 64 bits.

Cache (L1, L2, L3)

• High-speed memory on or close to the CPU.
• Bridges the speed gap between registers and RAM by holding frequently-used data/instructions for quick retrieval.
• Volatile.

• L1: typically 32 KB – 256 KB per core. Often separates data/instruction caches. 一个 core 一个。
• L2: typically 256 KB – 16 MB, per core or shared across multiple cores. 一个 core 一个或者多个 core share。
• L3: typically 2 MB – 32 MB, shared across all cores. 多个 core share。

Random Access Memory (RAM)

• The primary workspace — temporarily (volatile) stores the running OS, processes, and active data/instructions.

Type	Description
SRAM	Used in cache. Fast, stable, no refresh. Expensive, small capacity.
DRAM	Needs constant refresh. Slower. Large capacity, cheaper than SRAM.

Read-Only Memory (ROM)

• Non-volatile memory storing essential instructions/data for computer startup (e.g., BIOS, firmware 固件).
• Modifiable only through special processes.
• Used primarily for firmware storage — not part of the day-to-day register/cache/RAM hierarchy. Separate entity focused on boot-up (启动) and low-level startup operations.

CPU interaction with memory types

CPU ↔ Registers

• Direct interaction: CPU has internal registers — the fastest memory available. Store immediate data for current operations (operands, address pointers, results).
• Optimization: using registers for the most immediately-needed data minimizes access to slower memory → speeds processing.

CPU ↔ Cache (L1, L2, L3)

• Hierarchical use: cache is a high-speed intermediary between CPU and RAM.
  • L1: smallest capacity, fastest. L3: largest capacity, slowest — but still faster than RAM.
• Prefetching: modern CPUs use prediction algorithms to anticipate needed data/instructions and load them into cache early (提前) → reduces wait delays.
• Spatial and temporal locality (时间空间局部性): caches exploit spatial locality (nearby data likely accessed soon) and temporal locality (recently accessed data likely reused).

CPU ↔ Main Memory (RAM)

• Central data repository: RAM holds the OS, applications, and currently-used data. Much larger than caches/registers.
• Memory controller: CPU accesses RAM through the memory controller, which manages transfers, access timing, and data flow.
• Virtual memory (虚拟内存): uses part of the hard drive/SSD to extend system memory. CPU swaps data between RAM and virtual space — much slower than RAM.

CPU ↔ ROM

• Boot-up (start up): ROM stores firmware/BIOS used during startup. CPU reads this at boot (启动时) to initialize hardware and load the OS from secondary storage into RAM.

Cache miss and cache hit

• To fetch data/instruction, CPU checks registers → L1 → L2 → L3 → RAM.
  • Cache hit: data found in cache → very fast access.
  • Cache miss: data not found → CPU must fetch from RAM → slower.
• Techniques to reduce cache misses:
  • Prefetching: predicting and loading needed data early.
  • Smart memory allocation: placing data to improve hit rates.
  • Cache replacement policies: deciding which data to remove when cache is full.