Describe the fetch, decode and execute cycle

• Fetch: CPU fetches an instruction from memory (RAM).
• Decode: CPU interprets the instruction into low-level operations it can execute.
• Execute: CPU carries out the low-level operations specified by the decoded instruction.

Fetch Phase

CPU retrieves a machine-language instruction from main memory (RAM): CPU requests instruction from RAM; address goes to MAR; fetched instruction transfers to IR.

1. Address Identification: PC’s address moves to MAR (internal CPU bus).
2. Address Transmission: MAR puts address on the Address Bus (unidirectional, CPU → RAM).
3. Command Issuance: CU asserts a $\text{READ}$ signal on the Control Bus.
4. Data Retrieval: RAM receives address + READ command, places instruction onto Data Bus (instructions and data both known as data).
5. Data Reception: Instruction travels Data Bus (bidirectional) into MDR. → MDR holds instruction/data transferred to/from memory.
6. Instruction Loading: Instruction transfers from MDR to IR for the rest of the cycle. → IR holds the current instruction being executed.
7. Preparation: PC is incremented to the next instruction address (usually automatic).

Decode Phase

CPU interprets the machine-language instruction. Mostly done by the CU, which analyzes:

• Opcode (operation code): dictates (规定) the type of operation
• Operands: the data/address to be operated on
• Addressing Modes: determine how to load the operands

Process — the CU interprets the instruction in IR and determines execution steps:

1. Instruction Analysis: CU examines instruction in IR; parses Opcode (e.g., $\text{ADD, STORE}$) and Operand.
2. Control Signal Preparation: CU generates the micro-operation sequence (control signals) for Execute phase. Transmitted via Control Bus.
3. Address Staging: If the instruction needs RAM data (e.g., $\text{ADD}$) or writes back (e.g., $\text{STORE}$), the operand address moves from IR into MAR. ACC remains static this phase.

Execute Phase

CPU performs the operation specified by the opcode. Common operations:

• Arithmetic: addition, subtraction, multiplication, division (done by ALU).
• Logical: $\text{AND}$, $\text{OR}$, $\text{NOT}$ (done by ALU).
• Memory Access: load (read from memory to register) and store (write from register to memory).
• Control: conditional/unconditional jumps that alter execution flow.

Process — CU coordinates components based on instruction type:

A. Data Transfer to/from RAM (e.g., $\text{LOAD}$, $\text{STORE}$)

• MAR sends data address → Address Bus.
• CU asserts $\text{READ}$ or $\text{WRITE}$ → Control Bus.
• $\text{LOAD}$: RAM → Data Bus → MDR → ACC.
• $\text{STORE}$: ACC → MDR → Data Bus → RAM.

B. Arithmetic/Logic Operations (e.g., $\text{ADD}$, $\text{AND}$)

• Data sources (often ACC and MDR with data from RAM) supplied to ALU via internal CPU bus.
• CU sends the operation command (e.g., $\text{ADD}$) to ALU via Control Bus.
• ALU performs the calculation.
• Result written back to ACC, ready for next operation.

Cycle Completion: CU signals end of cycle; CPU loops back to Fetch using updated PC.

Examples of the FDE Cycle

(1) WRITE Value 0x7E to Address 0x4F2

1. FETCH Phase — Getting the Instruction

1. $[\text{PC}]$ ($\text{0x100}$) $\to \text{MAR}$ (Internal CPU Bus).
2. $[\text{PC}] + 1 \to \text{PC}$ ($\text{0x101}$).
3. $[\text{MAR}] \to$ Address Bus.
4. CU sends $\text{READ}$ $\to$ Control Bus.
5. $\text{RAM[0x100]} \to$ Data Bus $\to \text{MDR}$.
6. $[\text{MDR}] \to \text{IR}$ (Internal CPU Bus).

2. DECODE Phase — Setting Up the Write

1. CU decodes $\text{STA}$ from IR; identifies as $\text{WRITE}$.
2. $[\text{IR}_{Operand}]$ ($\text{0x4F2}$) $\to \text{MAR}$.
3. $[\text{ACC}]$ ($\text{0x7E}$) $\to \text{MDR}$.

3. EXECUTE Phase — Writing to Memory

1. $[\text{MAR}]$ ($\text{0x4F2}$) $\to$ Address Bus.
2. CU sends $\text{WRITE}$ $\to$ Control Bus.
3. $[\text{MDR}]$ ($\text{0x7E}$) $\to$ Data Bus.
4. RAM receives address, command, and data.
5. $\text{RAM[0x4F2]}$ is set to $\text{0x7E}$.

Cycle Complete

• CU signals end of cycle.
• CPU loops back to FETCH using $[\text{PC}]$ ($\text{0x101}$).

(2) Comparison Instruction: $\text{CMP R1, R2}$

Compare R1 with R2. Result only sets CPU Status Flags (Zero, Carry, etc.); no register receives the output.

1. FETCH Phase

1. $[\text{PC}]$ ($\text{0x300}$) $\to \text{MAR}$.
2. $[\text{PC}] + 1 \to \text{PC}$ ($\text{0x301}$).
3. $[\text{MAR}] \to$ Address Bus.
4. CU sends $\text{READ}$ $\to$ Control Bus.
5. $\text{RAM[0x300]} \to$ Data Bus $\to \text{MDR}$.
6. $[\text{MDR}] \to \text{IR}$ ($\text{CMP R1, R2}$ now in IR).

2. DECODE Phase

1. CU decodes $\text{CMP}$ from IR.
2. Identifies it as an ALU op requiring R1 and R2.
3. Prepares signals to use ALU for subtraction; result is not stored in a register like ACC.

3. EXECUTE Phase

1. Preparation: $[\text{R1}]$ ($15$) and $[\text{R2}]$ ($10$) → ALU inputs. Comparison = subtraction: $\text{R1} - \text{R2}$.
2. ALU Operation: CU sends $\text{SUBTRACT}$ → ALU via Control Bus.
3. Result and Flags: ALU computes $15 - 10 = 5$.
   • Arithmetic result ($5$) is discarded.
   • The condition is used by ALU to set CPU Status Flags.
4. Flag Setting (result = 5, positive, non-zero):
   • Zero Flag cleared (0).
   • Carry Flag (Borrow) cleared (0, unsigned).
   • Sign/Negative Flag cleared (0).
5. Control Flow Enablement: these flags now enable conditional instructions ($\text{BGT}$, $\text{BLE}$, etc.) to alter PC based on this comparison.

Cycle Complete

• CU signals cycle end.
• CPU begins next FETCH from $[\text{PC}]$ ($\text{0x301}$).